A Deep Review of Hardware Trojan Identification Methods in System-on-Chip Architecture

Abstract

Hardware Trojans (HTs) have become one of the most important dangers to the modern integrated circuits, particularly as System-on-Chip (SoC) designs are becoming both larger and more complex and dependent on globalized supply chains. Such malicious modifications may undermine functionality, cause sensitive information to get stolen, or provide backdoors that may remain unnoticed, and that means that effective detection methods are necessary to ensure that modern hardware platforms are secure. The higher diversification of chip architectures such as digital, analog or mixed-signal, RF as well as biochips also contributes to increased pressure on the security mechanisms that are robust and adaptive. A broad overview of hardware Trojan detection methods is presented in this work, especially paying attention to machine learning (ML) and deep learning (DL) development. Look at the pre-silicon (static and dynamic) verification schemes, post-silicon (side channels) and the new smart detection schemes that make use of the power, electromagnetic, timing, and PUF-based signals. Other issues that were identified in the survey are the computational overhead, data limitations and the cross-platform generalization problems. Overall, the work provides the existing advancement and trace the way to advance further research to enhance trusted SoC design and the security of hardware.