Synthetic Defect Data Generation Using Deep Learning Architecture for Improved Wafer Inspection Performance

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Roopesh Kumar

Abstract

Wafer defects have become smaller and more complex, increasing the demand for accurate and real-time quality monitoring and control. Wafer surface flaws can be properly inspected to detect defects in the production process faster. Hence, it is essential to have defect checking in the fabrication of the wafer to foster high productivity, cost effectiveness, and ideal performance. This paper provides an efficient wafer defect inspection model based on a Graph Neural Network (GNN) on the Mixed-type Wafer Defect Dataset of Kaggle that comprises some 38,000 wafer maps in 38 different, normal, single-defect, and mixed-defect classes. The wafer maps in the form of 52 ×52 grids were first processed into matrix normalization, handled labels with label encoder, reshaping, and graph-based representation to maintain the spatial relationships between dies. Stratified sampling was used to divide the dataset into training, validation and testing sets, and data augmentation was used, which included rotation, flipping and cropping to improve robustness and generalization. The suggested GNN has used message-passing and global pooling, which captures complex spatial and relationship defects that are difficult to understand by normal CNN and machine learning methods. The evaluation of the performance was conducted based on accuracy, precision, recall, F1-score, and cross-entropy loss. The experimental results show that the proposed model offers a high classification accuracy of 97.25, a high level of precision (96.70%), recall (96.17%), and F1-score (96.44%). Comparative analysis reveals that the GNN is superior to the MobileNetV1, ResNet50 and SVM models. In general, the findings indicate the strength, consistency, and appropriateness of GNNs in complex multi-defect wafer inspection of semiconductor manufacturing.

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Research Paper

How to Cite

Synthetic Defect Data Generation Using Deep Learning Architecture for Improved Wafer Inspection Performance. (2026). Journal of Global Research in Electronics and Communications(JGREC), 2(2), 1-7. https://doi.org/10.5281/zenodo.18439502

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