A Review of Fault Simulation Techniques Focused on Stuck-At Models in Digital IC Testing

Abstract

Stuck-at fault models are also used to determine the test and reliability of digital integrated circuits (ICs), especially where manufacturing defects and failures due to aging can occur. This review paper has addressed the ATPG flows and fault simulation techniques associated with both stuck-at fault (SAF) and transition delay fault (TDF) models in order to reveal their importance for catching small delay defects (SDDs) which otherwise pass undetected by the usual testing. A comprehensive analysis of various ATPG flows like incremental, merged, and split-model methods shows the important role played by different fault models (SAF, TDF, static and dynamic crosstalk-aware faults) in the defect coverage of state-of-the-art semiconductor technology. The review also deals with the shortcomings of the conventional delay testing and suggests the use of faster-than-at-speed testing (FAST) and WeSPer as a metric for assessing test quality under varying clock frequencies to the end of motivating the use of those methods. Fault simulation techniques such as serial, parallel, deductive, differential, and concurrent testing are analyzed to get an insight about their efficiency and applicability in the current VLSI testing. After that, the paper dwells on the impact of digital IC testing over various areas spanning VLSI design validation, built-in self-test (BIST), and semiconductor manufacturing, hence illustrating the connection between improved fault modeling and simulation and the three factors of higher yield, reliability, and robust test strategies in nanoscale technologies.