Synthetic Defect Data Generation Using Deep Learning Architecture for Improved Wafer Inspection Performance. Journal of Global Research in Electronics and Communications(JGREC), [S. l.], v. 2, n. 2, p. 1–7, 2026. DOI: 10.5281/zenodo.18439502. Disponível em: https://jgrec.info/index.php/jgrec/article/view/106. Acesso em: 31 jan. 2026.