A Review of Fault Simulation Techniques Focused on Stuck-At Models in Digital IC Testing. Journal of Global Research in Electronics and Communications(JGREC), [S. l.], v. 1, n. 11, p. 20–24, 2025. DOI: 10.5281/zenodo.17852778. Disponível em: https://jgrec.info/index.php/jgrec/article/view/86. Acesso em: 10 dec. 2025.